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Physical Partitioning of Logical Functions in VLSI Chip Design

IP.com Disclosure Number: IPCOM000062839D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Van Dyke, PD [+details]

Abstract

Disclosed is a method for the functional partitioning of large, dense VLSI (very large-scale integration) chips, while keeping at a minimum the interconnecting wire lengths between partition centers and bounding I/O's (input/outputs). The design of large, dense VLSI chips usually implies implicit functional partitioning of logic circuitry into ALU (arithmetic and logic unit), registers, control, etc. In order to find the minimum interconnecting wire lengths, the positions of these logic functions must be interchanged many times. Upon each new interchange, the rectangular shapes of the logic functions must be recalculated to fit perfectly again into the rectangular chip. The method below accomplishes this end. Assume the chip has X,Y dimensions with four logic functions at the first hierarchical level. Fig.