Browse Prior Art Database

Parallel Interface Switching Mechanism

IP.com Disclosure Number: IPCOM000062858D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Georgiou, CJ [+details]

Abstract

Non-blocking switching of multiple sets of parallel interface lines is allowed by utilizing high-speed crosspoint switching chips, and the complexity of the switching matrix of known schemes is reduced, along with increasing system reliability. The parallel interface lines are grouped into ingoing and outgoing lines and are connected to the switch via two sets of latches, so that each interface line corresponds to a latch. The set of latches corresponding to the ingoing lines loads in parallel a shift register whose serial output is connected to a switching matrix of high-speed switching chips. Likewise, the set of latches corresponding to the outgoing lines is loaded in parallel from a shift register whose input is also connected serially to the switching matrix.