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Memory Chip Selection Circuit

IP.com Disclosure Number: IPCOM000062875D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Doerre, G [+details]

Abstract

The circuit in Fig. 1, with the segment enclosed in dotted lines repeated once for every bit in the chip selection address, and with all nodes N connected in parallel to the signal OUT, performs a fully decoded chip selection in the following manner: 1. If a bit in the chip selection address must be high for the chip to be selected, connect node A to ground, and node B to the chip selection address bit. 2. If a chip selection address bit (CSAB) is to be low for chip selection, connect node B to VH, and node A to the chip selection address bit. Now, raise d1, which has been low. For OUT to rise, all nodes A must be low, and all nodes B must be high. In case 1, A is low, but the chip selection address bit determines whether B is high. In case 2, B is high, but the CSAB determines whether A is low (Fig. 2).