Browse Prior Art Database

Cross-Boundary Storage Micro Word Lockout Mechanism for a Dual Stream Processor System

IP.com Disclosure Number: IPCOM000062892D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Campion, MJ Jackson, EW [+details]

Abstract

In a dual stream processor (DSP) system that supports storage read or write micro words (whose data being addressed may cross a CACHE page boundary), the possibility exists that a deadlock condition may arise over both processors contending for the same CACHE page. The deadlock condition may take one of two forms, neither of which allows any further progress by either processor through its instruction stream. 1) The CACHE page of interest is shuttled or "ping/ponged" back and forth between processors via a CACHE to CACHE transfer function. 2) The CACHE directory status is continually altered from Valid to Copy back to Valid on one processor and Invalid to Copy to Invalid on the other.