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Cache Addressing to Minimize Off-Boundary Breakage

IP.com Disclosure Number: IPCOM000062900D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Meltzer, D [+details]

Abstract

IBM System/370 architecture allows operand data to begin on any byte boundary and instruction text to begin on any half-word boundary. The conventional cache organization fetches and stores data only on double or quad word boundaries. This frequently gives rise to the necessity of doing two fetches from sequential double or quad word addresses in order to accumulate a word of data. Fig. 1 shows a simplified view of address generation in a conventionally organized machine. The address adder provides operand addresses which are sent to the cache and which are stored in Operand Address Registers. In addition, an instruction (I) fetch address register is either loaded from the address adder for taken branches or from an incrementer for sequential instruction fetching. Figs.