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Improved Parity Checking and Detection Disclosure Number: IPCOM000062911D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

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Aichelmann, FJ [+details]


This is a technique for improving a memory utilizing parity by being able to detect address misselection (write selection into the wrong location within a memory system). This is accomplished by assigning a different parity on unselected bytes and checking these via information included within control lines. Thus, an indication of errors is provided prior to the write selection of the memory arrays. Fig. 1 depicts a block diagram of a typical system utilizing a memory. Fig. 2 expands the basic system block diagram configuration to include the elements of improved parity checking. Fig. 3 describes the assignments (for a 4-byte data flow example) of address and control for various select operations. Fig.