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Testing the Dynamic Behavior of Semiconductor Circuits

IP.com Disclosure Number: IPCOM000062937D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Rausch, F [+details]

Abstract

For supplementing the quasi-static testing of semiconductor circuits by dynamic testing, a group of exclusive OR (XOR) circuits is arranged between the register for accommodating the test bit pattern and the inputs of the sample. The figure shows a block diagram. Register A, accommodating the test bit pattern, is followed by a group B of XOR circuits. Their outputs are connected to the inputs of the sample C, whose outputs are linked to register D accommodating the test result which is sampled by pulse E. For the quasi-static test, which proceeds in a known manner, no control pulse is applied to the linked second inputs of the XOR circuits. For dynamic testing, a control pulse F is fed to the second inputs of the XOR circuits. As a result, the test bit pattern in input register A is applied to the sample in an inverted form.