Measuring Mobile Ion Densities in MOS Structures
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18
Contamination in the gate dielectric of metal-oxide semiconductor (MOS) structures may lead to instabilities. A standard method of measuring such contamination is the current/voltage (I-V loop) technique, as described below. Fig. 1 shows a MOS test structure comprising a metal gate of, say, aluminum, an insulator of, say, SiO2, and an Si substrate. This struc ture is heated to a typical value of 200ŒC and subjected to a voltage, as shown in Fig. 2. First, a forward voltage ramp of 0.05 to 1 V/s is applied. Then, the structure is electrically stressed by applying a voltage of 1 to 3 MV/cm for 1 to 5 minutes. Stressing is followed by a backward voltage ramp having the same characteristics as the forward voltage ramp. Fig. 3 shows the current/voltage characteristic obtained by applying the voltage of Fig. 2 to the MOS structure.