Differential Cascode Circuit Dotting
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18
The circuits shown in the drawings allow OR and AND dotting functions to be performed with differential cascode circuits in such a way that the power, delay and silicium area factors are improved significantly. Fig. 1 shows the AND dot of two differential cascode circuits 1 and 2 having outputs A and B. This AND dot is performed by additional transistors T1, and the NAND dot is performed by means of transistors T2 and T3. In Fig. 2, transistors T4 and T5 perform the OR dot function of outputs A and B of circuits 1 and 2. This figure shows a data bus structure with several emitter followers connected to the bus, and a receiving circuit 3.