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Mosfet Channel Length Tolerance Improvement Disclosure Number: IPCOM000062955D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

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Alcorn, CN Kotecha, HN Pearson, SD [+details]


In conventional self-aligned silicon gate FET manufacturing processes such as is disclosed in U.S. Patent 3,986,903, a layer of silicon dioxide and a layer of polycrystalline silicon are laid down on top of the silicon semiconductor substrate and then a layer of photoresist is applied to the top and is patterned in the shape of the desired electrode. The photoresist masks an etching step to remove all of the polycrystalline silicon and silicon dioxide layers except those portions directly beneath the patterned photoresist.