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Self-Aligning Polysilicon Base and Emitter Transistor

IP.com Disclosure Number: IPCOM000062966D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Chu, SF Hwang, B Wang, W [+details]

Abstract

This article describes a method for fabricating polysilicon base and emitter structures in a self-aligning single polysilicon layer with nitride sidewalls separating extrinsic base and emitter regions. Fabrication by Oxide Sidewall (Fig. 1 through Fig. 10) 1. Fig. 1 shows an integrated circuit transistor formed to subcollector, isolation, and P-base level by conventional processes. 2. Apply a thick layer of photoresist and remove by photomask to define intrinsic transistor area (Fig. 2). 3. Etch away Si3N4, using photoresist as a mask (Fig. 3). 4. Low temperature chemical-vapor deposit SiO2 and etch-back to form oxide sidewalls (Fig. 4). Implant boron extrinsic base. 5. Planarize device surface by depositing a thick layer of photoresist or polyimide. Etch-back to expose oxide sidewalls (Fig. 5). 6.