Browse Prior Art Database

Logic Signature Application

IP.com Disclosure Number: IPCOM000062984D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Roche, P [+details]

Abstract

This article describes the application of a logic signature technique to the verification of the functioning of a programmable pattern generator. The pattern generator is the part of a memory tester which generates logical data patterns for checking the device under test. A pattern is a true table (logical) of thousands of states, and several patterns constitute a test sequence. As known, the signature of a shift register is the content of the latter when the gate goes off the same data stream to give the same signature. The gate signal (see figure) rises on the beginning of the sequence and falls off at the end. The signature is then read from the shift register content and compared to an expected signature. If they match, the sequence is good.