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Hardware Translation Lookaside Buffer Reload for an Inverted Page Table

IP.com Disclosure Number: IPCOM000063011D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Hester, PD Simpson, RO [+details]

Abstract

Virtual memory systems must provide translation logic to convert a virtual address to a real address. A Translation Lookaside Buffer (TLB) is frequently used for this purpose. Since the TLB can only maintain a small number of virtual to real translations the required virtual to real translations needed may not be in the TLB and it may be necessary to examine the main storage page table and update the TLB contents. If hardware is used to update the TLB, better performance can be obtained and the minimum set associativity requirement for software reload can be eliminated. The hardware for updating the TLB consists of a finite state machine which automatically accesses inverted page table entries and then updates the TLB, as required.