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Read-Modify-Write DATA Integrity

IP.com Disclosure Number: IPCOM000063013D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Freeman, CP [+details]

Abstract

Alpha particle and stuck fault failures occur in dynamic storage. Although standard ECC techniques correct single bit errors, regardless of cause, double bit errors cannot be corrected by single error correcting hardware. However, by adding a control line, Storage Exception Address Register (SEAR), RAS Mode Diagnostic Register (RMDR) and a checkbit multiplexer to the system described in [*], data integrity can be maintained on Read-Modify-Writes which have a double bit ECC error in the read data. Fig. 1 shows the storage controller data flow involved in a Read-Modify-Write (or Test and Set) operation. One cycle fetches the data from the array and stores it in the READ DATA REGISTER. The next cycle passes data through the ECC CORRECT logic to correct any single bit errors.