Browse Prior Art Database

Increased Performance Storage Interface

IP.com Disclosure Number: IPCOM000063018D
Original Publication Date: 1985-Jan-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Freeman, CP Wright, CG [+details]

Abstract

This Storage Interface is a bus architecture that overlaps accesses in an interleaved storage system, resulting in increased system performance. Conventional small systems use an asynchronous bus to store or fetch data, as shown in Fig. 1. Even though this bus is architected so that an interleaved array (two banks) can be attached, accesses to each array cannot be overlapped and a truly interleaved system cannot be implemented because the master device, i.e., system processor, DMA controller, etc., must hold the address and address strobe until READY is received from the storage controller indicating data is available to be read or has been stored; therefore, the opposite array cannot be accessed until the current array has been accessed and the proper bus turnaround performed. Fig.