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High Data Rate, Contention, Serial Bus System

IP.com Disclosure Number: IPCOM000063043D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Balliet, L Kurtz, HL [+details]

Abstract

This article describes a serial bus design that accomplishes parallel bus functions with high performance when the serial transfer rates are relatively high by utilizing clock superposition on data in one single cable. At the present time, the various functional components within the central electronic complex (CEC) of many computing systems are interconnected on a high speed, multiline, multileaved parallel bus, as illustrated in Fig. 1. They include processors 1, storage 2, and some level of I/O attachment function such as a direct device controller 3, or a channel to attach many devices 4 or an I/O subsystem 5 with a very high level of function. These facilities are then interconnected by a high speed parallel bus 6. The predominant function performed on the bus is a storage access, either for a read or a write.