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Lift-Off Mask Process for Minimum Pitch

IP.com Disclosure Number: IPCOM000063071D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Bertelsen, BI [+details]

Abstract

This article described a lift-off mask process for minimum conductor pitch. Lift-off, without a penalty in minimum pitch, provides freedom of choice of materials for the extremely small line widths and spaces of the next generations of integrated circuit wiring. A lift-off mask is created to be "tailored" to match the vacuum deposition angle at all points on a wafer. This is achieved by the following: 1. A planarizing, strippable layer (e.g., polyimide) is applied to the wafer and given a drying bake below the imidization temperature. 2. A thin silicon-rich layer (about 100 nm) is applied by any of several means, e.g., vacuum deposition of Si or SiO2, CVD (chemical vapor deposition) of SiO2, etc., to form a "non-erodable" mask layer. Or, it may be incorporated in the photoresist (to be applied next) formulation. 3.