Multifunction Microprocessor Interface Bus
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18
A multitude of various microprocessor functions are distributed to a variety of logic modules using a minimum of module I/O pins. A hardware bus structure is involved that takes advantage of mutually exclusive operations within a processor to produce a more efficiently packaged design. The microcode architecture of the processor is instrumental in developing this bus because it is also oriented towards performing multiple functions in mutually exclusive situations. Basically, the processor may be of the type described in the U. S. Patent 4,047,161. A distinct characteristic of the technology chosen for the processor lies in the area of available pins. Initial efforts to package the processor design may leave many internal circuits unused after all of the I/O pins have been consumed.