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Submicron Trench Isolation Process Without Using Planarizing Material

IP.com Disclosure Number: IPCOM000063079D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Codella, C Ogura, S Riseman, J Rovedo, N [+details]

Abstract

The process uses a preparatory oxidized aluminum layer and strip material to form spacer sidewalls in preparation for deep isolation trench etching. Instead of conventional complete wafer surface planarization, the area to be protected is converted to aluminum oxide that will not etch away during spacer removal. The process is as follows: Fig. 1 . Using conventional process steps, a pad of SiO2 is grown, Si3N4 deposited over it, then low pressure chemical vapor deposited SiO2 is deposited over this. The top SiO2 and Si3N4 layers will provide an etch mask during trench Si reactive ion etching (RIE) in later steps. An Al layer is deposited; then strip material and spacer are formed. Fig. 2 . The exposed Al is converted to Al2O3 by a conventional oxidation or anodization process.