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Self-Aligning Extrinsic Base Implant Enhanced Transistor

IP.com Disclosure Number: IPCOM000063133D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Dockerty, RC [+details]

Abstract

This process yields an improved transistor by reducing base resistance without an increase in CCB, CEB, or reducing BVEBO, by the use of self-aligning extrinsic base implant. The process follows: 1. Conventional or known processes are used through and including level 1 (silicon nitride). 2. Low pressure chemical vapor deposit (LPCVD) polysilicon 2. 3. Chemical vapor deposit oxide layer 3. 4. Mask-on photoresist 4, using negative of present contact opening mask. 5. Expose layer 4 using known processes. 5.1 Reactive ion etch (RIE) oxide layer 3 in CF4 . 6. Strip photoresist 4. 7. Anisotropically etch layer 2 in SF6/Cl2 with known pre-etch (oxide layer 3 is an etch mask). 8. Wet etch remaining layer 3. 9. Deposit LPCVD SiO2 . 10.