Browse Prior Art Database

HIGH TEMPERATURE GATE, SELF-ALIGNED GaAs MESFET

IP.com Disclosure Number: IPCOM000063138D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Rutz, RF [+details]

Abstract

A high speed GaAs MESFET using a refractory metal self-aligned gate is provided with high electrical conductivity in the gate metal and the ability of the device with the patterned gate metallurgy in place to withstand high temperature annealing without appreciably altering the electrical properties by using a W gate pattern as a cap in a later ion implantation annealing step. The procedure is as follows: First, either co-evaporate or co-sputter, a thin (N500-1500 ˜) layer of W-Si on a standard ion-implanted an annealed semi-insulating (S.I.) GaAs wafer. Second, a sputtered or evaporated N 5000 ˜ thick W gate pattern is formed by standard lift-off photolithographic techniques. The structure is illustrated in Fig. 1.