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Multi-Well Memory Device Disclosure Number: IPCOM000063141D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

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Chang, LL Fang, FF [+details]


A double potential well configuration embedded in the gate region of a field-effect device will provide an improved memory element. A voltage applied between the gate electrode and the surface channel controls the state of charge of the two wells, resulting in a differential electric dipole (WRITE) which can be monitored by the channel conductivity (READ). A third, middle potential well may be provided, which is essential to transferred electrons until an opposite voltage is applied (ERASE), and providing a large dipole change. This leads to a switching device with fast, stable and large-signal nonvolatile memory. The basic structure of an FET is shown in Fig. 1A of which the energy diagram of the composite gate containing a double potential well (A and B with spacing d) is illustrated in Fig. 1B.