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Synchronization of Refresh Address Counters in a Multibank Storage System Disclosure Number: IPCOM000063150D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

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Herrman, BD Maule, WE [+details]


A technique is described whereby one counter is used to refresh two storage banks, thereby reducing the amount of logic normally required. To increase the performance of central processing units (CPUs), a prefetch mechanism is installed to increase the speed of instruction fetches from memory, as shown in Fig. 1. This concept requires that storage be divided into two separate storage banks 10 and 11, so that two instructions may be fetched simultaneously. A high speed buffer is used to shorten the access time for the next instruction fetch. Separating the storage into two banks also allows refreshes to be hidden so as not to impact performance. While one storage bank is being accessed, the other can be refreshed.