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Circuit for High Performance Drivers Disclosure Number: IPCOM000063155D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

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Schettler, H [+details]


The disclosed circuitry provides an electronic chip-in-place test (ECIPT) [1] latch and off-chip driver electrically in parallel for high performance and logically in series for testability. In order to achieve improved testability of VLSI chips ECIPT may be utilized. The ECIPT concept may require an ECIPT latch in series with a driver. The additional delay in the data path caused by the latch is undesirable. Fig. 1 depicts in general a portion of the ECIPT concept. The driver circuit is in series with the master latch of the ECIPT latch. From a performance point of view, it would be very desirable to have the driver and the ECIPT latch in parallel in order to avoid the delay due to the latch. Fig. 2 depicts a circuit having a driver and an ECIPT latch in parallel (solid lines) for high speed driving.