Method of Improved Error Detection Using Multi-Level Residue Checking of Complementary Bases
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18
The need for increased availability and reduced downtime of computer systems has brought about an emphasis on methods of error detection in digital logic circuitry. The increasing use of VLSI chips further compounds this situation by allowing complex functions to be implemented with few chips. Detection of errors in straightforward data busses and arrays can be handled satisfactorily by well-known parity or syndrome bit techniques. Irregular functions (e.g., random logic) are much more difficult to equip with effective error detection circuitry without using an unreasonably large amount of hardware.