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High Speed Logic Implementation of the Heterostructure Bipolar Transistor

IP.com Disclosure Number: IPCOM000063160D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Tiwari, S [+details]

Abstract

Different compound semiconductor materials may be used to provide reproducible high-low barriers in Schottky transistor logic applications yielding the advantages of a high speed non-saturating circuit. An example circuit, as shown in Fig. 1, is illustrated in Fig. 2. The structure of Fig. 2 is fabricated using molecular beam epitaxy. In Fig. 1, for preventing the saturation of the transistor, a Schottky clamp of barrier height d1 < built-in voltage of the collector base junction is used. The signal is picked from the collector by Schottky diodes of barrier height d2 < d1 . Logic is implemented using wired AND configurations and the logic swing is N(d1 - d2). Fig. 2 is the implementation of this logic circuit. The collector region consists of two closely lattice-matched materials with a graded gap in between.