Browse Prior Art Database

Utilization-Based Prefetching

IP.com Disclosure Number: IPCOM000063165D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Liu, L [+details]

Abstract

Utilization properties are used to prefetch units of blocks in a memory hierarchy comprised of three levels: a main memory at level 3 (L3), a second level cache (L2) and a first level cache (L1). In computer storage hierarchies (e.g., caches, memories) the "blocks", e.g., cache lines, pages) are often not very well utilized, especially when block sizes are bigger (e.g., .5K - 4K). This poor utilization behavior causes redundant overhead in moving non-useful data between storage hierarchies. There are also designs (e.g., sectored caches) in which only the needed units of a block are brought when a miss occurs. Although the frequency of a redundant data move is reduced in such sectored design, the processor performance will suffer from response time penalties due to more frequent misses.