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High Density CMOS Standard Image

IP.com Disclosure Number: IPCOM000063168D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Bruss, A Gheewala, TR Hickson, JB Nair, R [+details]

Abstract

A method is described herein which provides high density in CMOS using an automated design method while providing high speed by allowing large width PMOS and NMOS transistors without any area penalty. Interest in CMOS (Complementary Metal Oxide Semiconductor) circuits for logic applications is increasing. CMOS combines high performance (fast switching speed) with very low power consumption per circuit. This combination makes CMOS more attractive than most other competing technologies for the next stage of VLSI (Very Large-Scale Integration). The current state-of-the-art VLSI technology is represented by NMOS (N-channel Metal Oxide Semiconductor) circuits.