Browse Prior Art Database

High Speed Charge-Pump

IP.com Disclosure Number: IPCOM000063198D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Gillingham, RD [+details]

Abstract

Hard and soft file adapters require a phase-locked loop (PLL) to separate clock and data information from encoded data. The PLLs require a charge-pump to convert logic signals to pulses of current. The pulse-width input to the charge-pump must be accurately reproduced by the pulse-width of the output current pulse. For hard files the pulse-widths can be as small as five nanoseconds or less. The logic signals are shown in Fig. 1. The output current, Icp, can be delayed from the logic input pulses, but must not be skewed. The High Gain signal should simply change the peak of the output current. In the integrated implementations of charge-pumps there have typically been three major problems: First, for OEM applications there is only a five-volt power supply.