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READ Head Switching

IP.com Disclosure Number: IPCOM000063207D
Original Publication Date: 1985-Feb-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Buhler, OR [+details]

Abstract

Disclosed is a read head switching circuit. The circuit shown in the figure accepts the control signals SELECT 0/SELECT 1, READ/WRITE, and WRITE FF. Under command of these signals, damping resistor and read/ write head 10 ("0") or damping resistor and read/write head 11 ("1") will perform the required read or write function. The circuit topology allows ease of integration. In the READ mode, amplifier 19 for R/W head "0" or amplifier 20 for R/W head "1" is energized by current switch 22. Only one amplifier may be on at a time as determined by the conduction state of transistors 34 and 35. In the WRITE mode, current switch 23, consisting of transistors 36 and 37, diverts current from both amplifiers and routes this amplifier bias current 38 to dummy amplifier 21. Amplifier 21 consists of transistors 57 and 58.