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Analysis of Logic Path Timing

IP.com Disclosure Number: IPCOM000063244D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Hall, MS Hitchcock, RB Rivero, JL [+details]

Abstract

A technique for analyzing logic path timing is accomplished by identifying logic blocks in the intersecting forward and backward cones and to chain these blocks so that a block-oriented algorithm can process them. Path delay analysis of logic for timing problems requires that the designer identify to the system performing the computations all the logic blocks in the logic path. This can be improved with a system that works from the starting and ending points of the logic path. With this kind of a system the designer specifies the starting point (i.e., a latch) for the path trace and the system identifies all the resulting end points (i.e., other latches). The designer then selects the end point (i.e., a latch) that he wants to complete the logic tree.