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Sidewall Channel-Stop Doping for Deep-Trench Isolation of FET Devices Disclosure Number: IPCOM000063245D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

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Taur, Y [+details]


This article relates generally to processes for forming deep-trench isolation for semiconductor devices and more particularly to a process for forming channel-stop regions in the sidewalls of deep trenches which are used to electrically isolate FET devices formed on a semiconductor chip. Deep-trench isolation, a new isolation technique in Very Large Scale Integration (VLSI) technology in which narrow grooves are etched in a silicon wafer and then refilled with a dielectric or polysilicon before planarization, allows higher packing density in submicron Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The technique can also eliminate "latch-up" in Complementary Metal Oxide Semiconductor (CMOS) devices if the trenches are deep enough to reach the heavily doped substrate of the wafer.