Browse Prior Art Database

Ghz Multiplexer/Demultiplexer Controller

IP.com Disclosure Number: IPCOM000063258D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Grasso, LJ Hoffman, DE [+details]

Abstract

High performance memory array test systems require the generation of very high speed timing control signals for data multiplexer [mux] and demultiplexer [demux] circuits necessary to maintain data flow between the memory tester pattern generator and the high speed pin electronics. The disclosed approach departs from the traditional use of a master/ slave D-type flip-flop by utilizing the master output, which is typically not available, as well as the slave output, to create two signals cycling through four unique states to control the mux/demux circuit, thereby requiring only one half of the usual data rate and half the number of flip-flops. A typical high performance memory test system is diagrammed in Fig.