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Dynamic Random-Access Memory Cell With a Three-Dimensional Storage Capacitor and Fabrication Process Therefor

IP.com Disclosure Number: IPCOM000063267D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Hsu, Y Lu, N [+details]

Abstract

This article relates to a Dynamic Random-Access Memory (DRAM) cell with increased capacitance and more particularly to a DRAM cell wherein the cell capacitor electrode is formed by an island of polycrystalline silicon disposed on the surface of a semiconductor substrate in insulated spaced relationship with the substrate. Still more particularly, it relates to a DRAM cell wherein an associated access transistor is disposed in a region of single crystal semiconductor grown alongside the island of polycrystalline silicon. A fabrication process is also disclosed. Referring now to Fig. 1, there is shown a cross-sectional view of a DRAM cell 1 which incorporates an access transistor 2 and a capacitor 3. The latter two devices are disposed on the surface of a substrate 4.