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Stair-Case Approximation to Bevel Technique

IP.com Disclosure Number: IPCOM000063272D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Bojarczuk, NA Gorey, EF Schneider, CP [+details]

Abstract

The bevel and strain technique "1" is a standard measurement used to determine the junction depth of an N-P or a P-N semiconductor structure. Likewise, the spreading resistance technique [2] is another well known means for determining the vertical doping profile of many semiconductor device structures, some of which contain N-P or P-N junctions. These two measurement techniques depend on the on-bevel carrier distribution, which can be distorted from the dopant atomic profiles, as disclosed in [3]. This article describes a solution to this problem by the creation of a stair-case structure through wet or dry etching, which enables the stair-case to act like a bulk semiconductor and not disturb the carrier concentration, as in the case of a mechanical bevel. Fig.