Machine Which Reduces Delay Penalties Due to Data Dependencies and Interlocks to Achieve High Performance
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
A hardware modification of a medium-size machine achieves high performance with a scheme which ignores logical interlocks and data dependencies while maintaining proper instruction execution. The following describes the sequence of operations necessary to implement the instruction processing: 1. Compare the fields of the instructions in order to detect Sink/Source dependencies (within the Decode cycle). 2. If no dependencies exist, then process the instructions as usual. 3. Else Mark the dependent instructions (interlocked). Decode the subsequent instructions and store their Sinks in a temporary register store (TRS) at the put-away cycle (if these Sinks are dependent on the interlocked instructions). 4.