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Defective MTL (I2l) Array Chip Screening by Added Test Circuits

IP.com Disclosure Number: IPCOM000063316D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Wong, RC [+details]

Abstract

This article describes the addition of certain test circuits to an existing MTL (I2L) array which allows for a more efficient screening of word line (WL) defects during test. By the use of these circuits specific data is purposely written into the array cells without WL switching, such that good array cells are 'disturbed' while defective cells are not. Test circuit requirements for an MTL (I2L) memory array, including the extra circuits (devices) T1, T2, T3 and T4, are illustrated in Fig. 1. Sixteen T3 circuits are necessary and one each of T1, T2 and T4. Key to the disclosed screening test is the setting up of the bit line (BL) voltage offset in a controlled manner.