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Low Voltage Inverter Circuit Modifications for Redundancy

IP.com Disclosure Number: IPCOM000063329D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Dorler, JA Michail, MS [+details]

Abstract

This article concerns the implementation of redundancy in low voltage inverter (LVI) circuits [1, 2] to improve chip yields through error recovery. One recognized disadvantage of redundancy, apart from the imposition of special requirements on LVI logic circuits, is increased wiring complexity which adds large capacitive loading to the logic cells, in turn causing unacceptable increases in circuit delay time. The disclosed LVI circuit modification allows for redundancy implementation with severe degradation in LVI circuit performance. Fig. 1 illustrates a logic path with NOR gates, implementing redundancy. A common wiring defect is shown in the figure, where a signal line short 1 exists between the output signal lines of gates #2 and #4, e.g.