Low Power Nmos Using LSSD Clocking Scheme
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
The concept disclosed is pulse powering the combinatorial logic block located between two LSSD (level sensitive scan design) shift registers with the timing of the power pulse coinciding with the C2 clock waveform for the slave latch in the LSSD shift registers. Referring to Fig. 1, it is seen that the eight-bit parallel input data flow to the LSSD shift register 1 is clocked into the master latch L11 through L18 during the interval between T4 and T5 in the timing diagram of Fig. 2. Then at time T6, the C2 clock waveform rises, transferring the latched data from the master latch L11 through L18 into the slave latch L21 through L28. It is at this time that the data is valid and input into the first stage of the N stage combinatorial logic block.