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Non-Clocked RAM Cell in CMOS Technology

IP.com Disclosure Number: IPCOM000063337D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Nuez, JP Piccino, C [+details]

Abstract

Shown in the drawing is a seven-device cell for a single- or a dualport non-clocked random-access memory in (CMOS) technology. The cell is comprised of two cross-coupled inverters during the read cycle. In write mode the loop is open to facilitate the write operation. T2, T4 and T7 are P-type transistors, and T1, T3, T5 and T6 are N-type transistors. For a single-port RAM, the possible states for transistors T5, T6 and T7 are as follows : (Image Omitted) The reading of the cell is made by sensing the middle node B of the two cross-coupled inverters through the transfer gate. In this state, access gate T6 is OFF, and T7 is ON. As these transistors are complementary, they are controlled by the same signal.