Browse Prior Art Database

Clock Checking

IP.com Disclosure Number: IPCOM000063344D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Dauby, A Poiraud, C [+details]

Abstract

The circuit shown in the drawing allows the clock phases used to generate the clock signals of a processor to be checked. Five clock phases P1 to P5 are used to generate the clock signals C of a processor. For instance, C1 is generated from P1=1 and P2=0, and C2 is generated from P3=1 and P4=0. These five phases have to be checked to guarantee a good clock generation, since if one of these phases were stuck at 0 or 1, the clock signals generated therefrom would not be correct. As shown in the timing diagram, there is one time when all the five phases are at 0 and another time when all the five phases are at 1. These two states are decoded. Latch L is set by State S "all 0" and reset by state R "all 1". If S and R states are present, latch L runs as a flip-flop and provides, at its output, waveform L.