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Full LDD Devices Fabricated by Photoresist Planarization Disclosure Number: IPCOM000063346D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

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Related People

Jaffe, D Lai, FS [+details]


This article relates generally to methods for fabricating integrated circuits incorporating metal-oxide-semiconductor field-effect transistors (MOSFET) and more particularly to a method for fabricating MOSFETs with lightly doped drains (LDD) using a thickness dependent exposure of planarized resist to form gate sidewall spacers. Referring now to Fig. 1, there is shown a cross-sectional view of a MOSFET 1 at an intermediate stage in its fabrication process. MOSFET 1, at this point, includes a polysilicon gate 2 disposed between a pair of recessed oxide (ROX) regions 3 in insulated spaced relationship with the surface of a semiconductor wafer by a thin layer 5 of silicon dioxide. Source/drain regions 6 of n- conductivity type are disposed in wafer 4 in self-aligned relationship with ROX regions 3 and polysilicon gate 2.