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READING OF A (n+1) BYTE COUNTER WITH A -n BYTE INTERFACE DATA BUS

IP.com Disclosure Number: IPCOM000063348D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Pin, C Poiraud, C Sazbon, D [+details]

Abstract

In a system wherein at least one adapter A communicates with a processor P via a n byte data bus, the proposal allows a (n+1) byte counter content to be sent to the processor. As shown in the drawing, a 3-byte counter is implemented in adapter A, connected to processor P by a 2-byte data bus. The counter has to be read by the processor through processor-initiated operation (PI0). As the counter is 3-byte large (byte 2, byte 1, byte 0) and the PI0 operation can read only two bytes, the reading must be done in two parts. A first operation PI0-1 transfers byte O and byte 1 from the adapter to the processor. A second operation PI0-2 transfers byte 2 to the processor.