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True/Complement Linear Feedback Shift Register Test Pattern Generator

IP.com Disclosure Number: IPCOM000063361D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Eichelberger, E Langmaid, R Lindbloom, E Waicukauski, J [+details]

Abstract

Linear feedback shift registers (LFSRs) which produce maximum length sequences can be used as sources of test patterns for logic devices, but if the device to be tested has more primary inputs and shift register latches (SRLs) than the length of the available LFSR generator, some test patterns needed to test the device cannot be generated. However, if the LFSR generator is used in both a true and a complement mode, missing test patterns can be recovered. Consider the following simple example. Take a four-bit LFSR generator configured as follows: (Image Omitted) and a device under test (DUT) having primary inputs (PIs) 1 through 5 and an AND gate driven by PIs 1, 4 and 5. (Image Omitted) The LFSR, when initialized, will step through the following states and produce the illustrated stream of test bits.