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Highly Planar Polysilicon-Base Transistor With Low Metal Land Capacitance

IP.com Disclosure Number: IPCOM000063380D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Jambotkar, CG [+details]

Abstract

The integrated circuit transistor process provides a near-ideal, highly planar polysilicon-base transistor structure. The disclosed process allows omission of the conventional recessed oxide, while yielding metal land capacitance which is lower than that obtained by using conventional recessed oxide. N+ subcollector regions 10 are formed in P- substrate (not shown) by conventional processes. This N+ doping can be a blanket deposition, assuming deep trench device isolations, which are not shown. N- epitaxial silicon film 11 is formed. SiO2 12 and Si3N4 13 represent conventional thin insulating layers at the N- epitaxial surface. N+ region 10 represents the conventional collector reach-through in the N- epitaxial layer 11.