Browse Prior Art Database

Self-Optimizing Computer Clock-Generation System

IP.com Disclosure Number: IPCOM000063384D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Koerner, S [+details]

Abstract

The computer clock-generation system of present machinery works from worst-case assumptions, generating clock frequencies that can still be processed by the slowest hardware. For adapting the clock frequency to actual performance, a control circuit is needed. On the clock chip, a ring oscillator 2 is integrated, the characteristic frequency of which is inversely proportional to the respective on-chip delay. A control logic 3 then selects the suitable machine clock frequency according to the frequency of a programmable ring oscillator 4. The clock chip and the chips in the critical paths of a machine must originate with the same hardware lot.