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TTL Delay PROM

IP.com Disclosure Number: IPCOM000063394D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Olsen, FW [+details]

Abstract

A transistor-transistor logic (TTL) delay programmable read-only memory (PROM) is designed to obtain a leading edge delay without causing trailing excessive delay. This programmable delay also has buffer output drive capability. To obtain a leading edge delay with a PROM (Fig. 1), program the PROM for sequential address access sequence, thereby achieving a leading edge delay equal to access time for each "feedback loop". The scheme of multiple access times is used as a delay circuit because of the sequential loops. Program output Q2 to 1 for A0 input high and with Q2 wired to A2; program Q3 to 1 for A2, A0 inputs high with Q3 wired to A3; program Q4 to 1 for A3, A2, A0 inputs high and with Q4 wired to A4; program Q1 to 1 for A4, A3, A2, A0 inputs high (Fig. 2).