Chip Select Decoder Circuit
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18
A simple chip select circuit is shown in the figure which is useful with a low complexity CPU-based system. The system includes a CPU 10, a random-access memory (RAM) I/O and timer circuit 12, a universal synchronous/asynchronous receiver transmitter (USART) circuit 14 and read-only memory circuit 16, all four of which may be coupled to a conventional computer bus 18 in a known manner. It is noted that memory 16 is connected through a series of latches 20 to the bus 18 in a known manner. Each of the components 12, 14 and 16 are operated in response to chip select (CS) signals applied thereto under the control of signals from CPU 10. The control signals from CPU 10 affecting the chip selects are the A15 signal, S1 signal, ALE signal, IO/M signal and RD signals.