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Serial or Random Access Memory Disclosure Number: IPCOM000063407D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

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Gray, KS [+details]


Present generation field-effect transistor (FET) random-access memory (RAM) chips have the typical commands and command coding (Table 1), and the refresh address counter (RAC) circuitry is implemented on the memory chip to keep track of the next word line to be refreshed. The RAC circuitry is a sequential counter that steps through the word lines on the memory chip. Three operations which are presently done are: 1. Regen (regeneration) using RAC word line address, no data output. 2. Write with input address. 3. Read with input address. These will be referred to as the normal read, normal write, and normal Regen functions of the RAM chip. Using the proposed typical FET RAM commands and command coding (Table 2) results in major FET RAM chip improvements. The three commands used are: 1.