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Self-Timed Data Out Driver

IP.com Disclosure Number: IPCOM000063409D
Original Publication Date: 1985-Mar-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Ellis, WF [+details]

Abstract

Fig. 1 shows a 5V Data I/O circuit where capacitor C1N and transistors 1N-1ON C1N-9N have been added to facilitate a Data Latch T Data-Out interlock. Functions: RESTORE - For a RESTORE or RAS (Row Address Strobe) only REFRESH Cycle (RC) stays high, resulting in nodes N and I1 being held to ground through their respective pass devices. Node B is held high by transistor (T)5N. The Data-Latch nodes, DL and DR, are restored to VH. The CAS phases d1C-d4C remain inactive. READ "1" - For a READ "1", RC falls at the beginning of the cycle. Later, 3C charges node N to VH through T1N, which self-boosts. At d4C, the Data-Latch sets, pulls DL low. Also, T3N pulls the gate of T1N to ground and node I1 rises, turning on the isolation devices TI1 and TI2. As DL falls to ground, it pulls node N down through TI1.